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| 250 ksps, 6-channel,simultaneous sampling, bipolar 12/14/16-bit adc preliminary technical data ad7658/ad7657/ad7656* rev. pri information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features 6 independent adcs true bipolar analog inputs pin/software selectable ranges:- 10v, 5v fast throughput rate: 250 ksps specified for v cc of 4.5 v to 5.5 v low power 160mw at 250 ksps with 5 v supplies wide input bandwidth: 85 db snr at 50 khz input frequency on-chip reference and reference buffers parallel and serial interface high speed serial interface spi/qspi/wire/dsp compatible standby mode: 5 a max i cmos tm process technology 64 lqfp package applications power line monitoring systems instrumentation and control systems multi-axis positioning systems functional block diagram 16-bit sar buf agnd dgnd v 1 av cc sclk d out b ad7656 output drivers control logic t/h v drive ser/par v dd ref v ss t/h t/h t/h t/h t/h v 2 16-bit sar 16-bit sar 16-bit sar 16-bit sar 16-bit sar v 3 v 4 v 5 v 6 data/ control lines output drivers d out c output drivers output drivers clk osc convsta convstb convstc dv cc figure 1. general description the ad7658/ad7657/ad7656 contai n six 12/14/16-bit, fast, low power, successive approximation adcs all in the one package. the ad7658/ad7657/ad7656 core operates from a single 4.5 v to 5.5 v power supply and features throughput rates up to 250 ksps. the parts contain low noise, wide bandwidth track-and- hold amplifiers that can handle input frequencies up to 8 mhz. the conversion process and data acquisition are controlled using convst signals and an internal oscillator. three convst pins allow independent simultaneous sampling of the three adc pairs. the ad7658/ad7657/ad7656 have both a high speed parallel and serial interface allowing the devices to interface with microprocessors or dsps. when in serial interface mode these parts have a daisy chain feature allowing multiple adcs to connect to a single serial interface. the ad7658/ad7657/ad7656 can accommodate true bipolar input signals in the 10v range and 5v range . they contain a 2.5v internal reference and can also accept an external reference. if a 3v external reference is applied to the vref pin, the adcs can accommodate a true bipolar 12v analog input range. v dd and v ss supplies of 12v are required for this 12v input range. product highlights 1. six 12/14/16-bit 250 ksps adcs on board. 2. six true bipolar high impedance analog inputs. 3. the ad7658/ad7657/ad7656 feature both a parallel and a high speed serial interface. * protected by u.s. patent no. 6,731,232 i cmos tm process technology for analog systems designers within industrial/instrumentation eq uipment oems who need high performance ics at higher-voltage l evels, i cmos is a technology platform that enables the development of analog ics capable of 30v and operating at +/- 15v supplies while allowing dramatic reductions in power consumption and package size, and increased ac and dc performance.
ad7658/ad7657/ad7656 preliminary technical data rev. pri | page 2 of 25 table of contents ad7658 specifications..................................................................... 3 ad7657 specifications..................................................................... 5 ad7656 specifications..................................................................... 7 timing specifications....................................................................... 9 absolute maximum ratings.......................................................... 10 esd caution................................................................................ 10 pin functional descriptions ..................................................... 11 terminology .................................................................................... 14 converter details.......................................................................... 15 track-and-hold section........................................................ 15 analog input section ............................................................. 15 adc transfer function............................................................. 16 interface section.......................................................................... 17 parallel interface (ser/ par = 0) ......................................... 17 software selection of adcs.................................................. 18 changing the analog input range( h /s sel=0)................ 18 changing the analog input range( h /s sel=1)................ 19 serial interface (ser/ par = 1) ................................. 19 serial read operation ........................................................... 20 daisy-chain mode(dcen =1, ser/ par = 1) ................... 20 standby/partial power down modes of operation........... 23 ordering guide .......................................................................... 25 revision history revision pri: preliminary version preliminary technical data ad7658/ad7657/ad7656 rev. pri | page 3 of 25 ad7658 specifications 1 table 1. av cc = 4.5 v to 5.5 v, v dd = 9.5 v to 16.5 v, v ss = -9.5 v to -16.5v, dv cc = 4.5 v to 5.5 v, v drive = 2.7v to 5.25v, f sample = 250 ksps, vref = 2.5v internal/external, unless otherwise noted; t a = t min to t max , unless otherwise noted parameter b versions 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise + distortion (sinad) 2 70 db min 71 db typ total harmonic distortion (thd) 2 ?92 db typ peak harmonic or spurious noise (sfdr) 2 ?-tbd db typ intermodulation distortion (imd) 2 second-order terms ?94 db typ third-order terms ?100 db typ aperture delay 20 ns max aperature delay matching 2 ns max 100 ps typ aperture jitter 30 ps typ full power bandwidth 8 mhz typ @ ?3 db 2.2 mhz typ @ ?0.1 db dc accuracy no missing codes 12 bits min integral nonlinearity 2 1 lsb typ positive full scale error 2 0.4 % fs max bipolar zero error 2 2.1 mv max v dd = 5.5 v negative full scale error 2 0.4 % fs max analog input input voltage ranges 4xvref v rng bit/range pin = 0 2xvref v rng bit/range pin = 1 dc leakage current 0.3 a max input capacitance 30 pf typ reference input/output reference output voltage 2.49/2.51 v min/max reference input voltage range 2.5/3 v min/max dc leakage current 0.5 a max v ref pin input capacitance 20 pf typ v ref output impedance 1 kohms typ reference temperature coefficient 25 ppm/c max 10 ppm/c typ logic inputs input high voltage, v inh 0.7 x v drive v min input low voltage, v inl 03 x v drive v max input current, i in 0.3 a max typically 10 na, v in = 0 v or v cc input capacitance, c in 3 10 pf max logic outputs output high voltage, v oh v drive C 0.2 v min i source = 200 a; output low voltage, v ol 0.4 v max i sink = 200 a floating-state leakage current 0.3 a max floating-state output capacitance 3 10 pf max output coding twos complement conversion rate conversion time 3 s max track-and-hold acquisition time 400 ns max throughput rate 250 ksps power requirements v dd +9.5v/+16.5v v min/max ad7658/ad7657/ad7656 preliminary technical data rev. pri | page 4 of 25 parameter b versions 1 unit test conditions/comments v ss -9.5v/-16.5v v min/max av cc 4.5/5.5 v min/v max i dd digital i/p s = 0 v or v cc normal mode (static) 40 ma max sclk on or off. v cc = 5.5 v normal mode (operational) 35 ma max f sample = 250 ksps. v cc = 5.5 v full power-down mode 5 a max sclk on or off. v cc = 5.5 v power dissipation v cc = 5.5 v normal mode (operational) 192.5 mw max f sample = 250 ksps full power-down 16.5 w max 1 temperature range as follows: b version: ?40c to +85c. 2 see terminology section. 3 sample tested during initial release to ensure compliance. preliminary technical data ad7658/ad7657/ad7656 rev. pri | page 5 of 25 ad7657 specifications 1 table 2. av cc = 4.5 v to 5.5 v, v dd = 9.5 v to 16.5 v, v ss = -9.5 v to -16.5v, dv cc = 4.5 v to 5.5 v, v drive = 2.7v to 5.25v, f sample = 250 ksps, vref = 2.5v internal/external, unless otherwise noted; t a = t min to t max , unless otherwise noted parameter b versions 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise + distortion (sinad 2 81 db min signal-to-noise ratio (snr) 2 82 db min 83 db typ total harmonic distortion (thd) 2 ?97 db typ peak harmonic or spurious noise (sfdr) 2 ?95 db typ intermodulation distortion (imd) 2 second-order terms ?94 db typ third-order terms ?100 db typ aperture delay 20 ns max aperature delay matching 2 ns max 100 ps typ aperture jitter 30 ps typ full power bandwidth 8 mhz typ @ ?3 db 2.2 mhz typ @ ?0.1 db dc accuracy no missing codes 14 bits min integral nonlinearity 2 1.5 lsb typ positive full scale error 2 0.4 % fs max bipolar zero error 2 2.1 mv max v dd = 5.5 v negative full scale error 2 0.4 % fs max analog input input voltage ranges 4xvref v rng bit/range pin = 0 2xvref v rng bit/range pin = 1 dc leakage current 0.3 a max input capacitance 30 pf typ reference input/output reference output voltage 2.49/2.51 v min/max reference input voltage range 2.5/3 v min/max dc leakage current 0.5 a max v ref pin input capacitance 20 pf typ v ref output impedance 1 kohms typ reference temperature coefficient 25 ppm/c max 10 ppm/c typ logic inputs input high voltage, v inh 0.7 x v drive v min input low voltage, v inl 0.3 x v drive v max input current, i in 0.3 a max typically 10 na, v in = 0 v or v cc input capacitance, c in 3 10 pf max logic outputs output high voltage, v oh v drive C 0.2 v min i source = 200 a; output low voltage, v ol 0.4 v max i sink = 200 a floating-state leakage current 0.3 a max floating-state output capacitance 3 10 pf max output coding twos complement conversion rate conversion time 3 s max track-and-hold acquisition time 500 ns max throughput rate 250 ksps power requirements ad7658/ad7657/ad7656 preliminary technical data rev. pri | page 6 of 25 parameter b versions 1 unit test conditions/comments v dd +9.5v/+16.5v v min/max v ss -9.5v/-16.5v v min/max av cc 4.5/5.5 v min/v max i dd digital i/p s = 0 v or v cc normal mode (static) 40 ma max sclk on or off. v cc = 5.5 v normal mode (operational) 35 ma max f sample = 250 ksps. v cc = 5.5 v full power-down mode 5 a max sclk on or off. v cc = 5.5 v power dissipation v cc = 5.5 v normal mode (operational) 192.5 mw max f sample = 250 ksps full power-down 16.5 w max 1 temperature range as follows: b version: ?40c to +85c. 2 see terminology section. 3 sample tested during initial release to ensure compliance. preliminary technical data ad7658/ad7657/ad7656 rev. pri | page 7 of 25 ad7656 specifications 1 table 3. av cc = 4.5 v to 5.5 v, v dd = 9.5 v to 16.5 v, v ss = -9.5 v to C16.5v, dv cc = 4.5 v to 5.5 v, v drive = 2.7v to 5.25v, f sample = 250 ksps, vref = 2.5v internal/external, unless otherwise noted; t a = t min to t max , unless otherwise noted parameter b versions 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise + distortion (sinad) 2 82.5 db min 85 db typ signal-to-noise ratio (snr) 2 83 db min 86 db typ total harmonic distortion (thd) 2 ?97 db max peak harmonic or spurious noise (sfdr) 2 ?95 db typ intermodulation distortion (imd) 2 second-order terms ?94 db typ third-order terms ?100 db typ aperture delay 20 ns max aperature delay matching 2 ns max 100 ps typ aperture jitter 30 ps typ full power bandwidth 8 mhz typ @ ?3 db 2.2 mhz typ @ ?0.1 db dc accuracy no missing codes 15 bits min integral nonlinearity 2 2 lsb typ 4 lsb max positive full scale error 2 0.4 % fs max bipolar zero error 2 2.1 mv max v dd = 5.5 v negative full scale error 2 0.4 % fs max analog input input voltage ranges 4xvref v rng bit/range pin = 0 2xvref v rng bit/range pin = 1 dc leakage current 0.3 a max input capacitance 30 pf typ reference input/output reference output voltage 2.49/2.51 v min/max reference input voltage range 2.5/3 v min/max dc leakage current 0.5 a max v ref pin input capacitance 20 pf typ v ref output impedance 1 kohms typ reference temperature coefficient 25 ppm/c max 10 ppm/c typ logic inputs input high voltage, v inh 0.7 x v drive v min input low voltage, v inl 0.3 x v drive v max input current, i in 0.3 a max typically 10 na, v in = 0 v or v cc input capacitance, c in 3 10 pf max logic outputs output high voltage, v oh v drive C 0.2 v min i source = 200 a; output low voltage, v ol 0.4 v max i sink = 200 a floating-state leakage current 0.3 a max floating-state output capacitance , 3 10 pf max output coding twos complement conversion rate conversion time 3 s max track-and-hold acquisition time 1 s max throughput rate 250 ksps ad7658/ad7657/ad7656 preliminary technical data rev. pri | page 8 of 25 parameter b versions 1 unit test conditions/comments power requirements v dd +9.5v/+16.5v v min/max v ss -9.5v/-16.5v v min/max av cc 4.5/5.5 v min/v max i dd digital i/p s = 0 v or v cc normal mode (static) 40 ma max sclk on or off. v cc = 5.5 v normal mode (operational) 35 ma max f sample = 250 ksps. v cc = 5.5 v full power-down mode 5 a max sclk on or off. v cc = 5.5 v power dissipation 4 v cc = 5.5 v normal mode (operational) 192.5 mw max f sample = 250 ksps full power-down 16.5 w max 1 temperature range as follows: b version: ?40c to +85c. 2 see terminology section. 3 sample tested during initial release to ensure compliance. v preliminary technical data ad7658/ad7657/ad7656 rev. pri | page 9 of 25 timing specifications 1 table 4. av cc = 4.5 v to 5.5 v, v dd = 9.5 v to 16.5 v, v ss = -9.5 v to -16.5v, v drive = 2.7v to 5.25v; t a = t min to t max , unless otherwise noted limit at t min, t max parameter 5 v unit description parallel mode t convert 3 s typ conversi on time, internal clock t quiet 400 ns min minimum quiet time required between bus relinquish and start of next conversion t 1 3 ns min convst high to busy high t wake-up tbd ns typ stby rising edge to convst rising edge write operation t 13 0 ns min cs to wr setup time t 14 0 ns min cs to wr hold time t 12 20 ns min wr pulse width t 15 5 ns min data setup time before wr rising edge t 12/14/16 5 ns min data hold after wr rising edge read operation t 2 0 ns min busy to rd delay t 3 0 ns min cs to rd setup time t 4 0 ns min cs to rd hold time t 5 30 ns min rd pulse width t 6 30 ns max data access time after rd falling edge t 7 15 ns min bus relinquish time after rd rising edge 25 ns max t 9 20 ns min minimum time between reads serial interface f sclk 20 mhz max frequency of serial read clock t 17 10 ns max cs to sclk setup time t 18 15 ns max delay from cs until sdata three-state disabled t 19 20 ns max data access time after sclk rising edge t 20 0.4 t sclk ns min sclk low pulse width t 21 0.4 t sclk ns min sclk high pulse width t 22 5 ns min sclk to data valid hold time t 23 30 ns max cs rising edge to sdata high impedance 03643-0-002 200 ai ol 200 ai oh 1.6v to output pin c l 50pf figure 2. load circuit for digital output timing specification 1 sample tested during initial release to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. ad7658/ad7657/ad7656 preliminary technical data rev. pri | page 10 of 25 absolute maximum ratings table 5. t a = 25c, unless otherwise noted parameter rating v dd to agnd, dgnd -0.3 v to +16.5 v v ss to agnd, dgnd +0.3 v to C16.5 v v cc to agnd, dgnd -0.3v to +7v v drive to v cc -0.3 v to v cc + 0.3v agnd to dgnd -0.3 v to +0.3 v v drive to dv dd -0.3 v to dv dd + 0.3v analog input voltage to agnd v ss C 0.5v to v dd + 0.5v digital input voltage to dgnd -0.3 v to v drive +0.3 v digital output voltage to gnd -0.3 v to v drive +0.3v ref in to agnd -0.3 v to v cc +0.3v input current to any pin except supplies 2 10ma operating temperature range -40c to +85c storage temperature range -65c to +150c junction temperature +150c 64-lqfp package, power dissipation ja thermal impedance tbdc/w jc thermal impedance tbdc/w pb-free temperature, soldering reflow 260(+0)c esd tbd kv 1 transient currents of up to 100 ma will not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. preliminary technical data ad7658/ad7657/ad7656 rev. pri | page 11 of 25 pin functional descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pin 1 identifier db7/hben/dcen db6/sclk db5/dcin a db4/dcin b db3/dcin c db2/sel c db1/sel b vdrive db13 db12 db11 db10/sdata c db9/sdata b db8/sdata a dgnd db14/refbuf en/dis range dvcc reset w/b vss vdd agnd dgnd busy cs rd convst c convst b convst a stby db0/sel a v3 agnd agnd v2 avcc avcc v1 avcc avcc avcc v5 agnd agnd v4 avcc v6 agnd agnd agnd refin/refout avcc agnd refcapb h/s sel ser/par sel avcc agnd refcapc agnd db15 wr/ref en/dis refcapa table 6. ad7658/ad7657/ad7656 pin fu nction descriptions pin mnemonic description refcapa, refcapb, refcapc decoupling capacitors are connec ted to these pins to decouple the reference buffer for each adc pair. each refcap pin should be decoupled to agnd using 10 f and 100 nf capacitors. v1 C v6 analog input1-6. these are six single-ended an alog inputs. the analog input range on these channels is ddetermined by the range pin. agnd analog ground. ground reference point for all analog circuitry on the ad7658/ad7657/ad7656. all analog input signals and any external reference signal should be referred to this agnd voltage. all eleven of these agnd pins should be connected to the agnd plane of a system. the agnd and dgnd voltages ideally should be at the same potential and must not be more than 0. 3 v apart, even on a transient basis. dvcc digital power. normally at 5v. the dvcc and av cc voltages should ideally be at the same potential and must not be more than 0.3 v apar t even on a transient basis. this supply should be decoupled to dgnd. 10 f and 100 nf decoup ling capacitors should be placed on the dvcc pin. vdrive logic power supply input. the voltage supplied at this pin determines at what voltage the interface will operate. nominally at the same su pply as the supply of the host interface. this pin should be decoupled to dgnd. 10 f and 1 00 nf decoupling capacitors should be placed on the vdrive pin. ad7658/ad7657/ad7656 preliminary technical data rev. pri | page 12 of 25 dgnd digital ground. this is the ground refere nce point for all digital circuitry on the ad7658/ad7657/ad7656. both dgnd pins should connect to the dgnd plane of a system. the dgnd and agnd voltages ideally should be at the same potential and must not be more than 0.3 v apart even on a transient basis. avcc analog supply voltage, 4.5 v to 5.5 v. this is the only supply voltage for adc cores. the avcc and dvcc voltages ideally should be at the same potential and must not be more than 0.3 v apart even on a transient basis. this supply sh ould be decoupled to agnd. 10 f and 100 nf decoupling capacitors should be placed on the avcc pins. convsta, b, c conversion start input a,b,c. logi c inputs. these inputs are used to initiate conversions on the adc pairs. convsta is used to initiate simult aneous conversions on v1 and v2. convstb is used to initiate simultameous conversions on v3 and v4. convstc is used to initiate simultaneous conversions on v5 and v6. when convstx switches from low to high the track- and-hold switch on the selected adc pairs switches from track to hold and the conversion is initiated. cs chip select. active low logic input. this input frames the data transfer. when both cs and rd are logic low in parallel mode the output bus is enabled and the conversion result is output on the parallel data bus lines. when both cs and wr are logic low in parallel mode db[15:8] are used to write data to the on-chip co ntrol register. in serial mode the cs is used to frame the serial read transfer. rd read data. when both cs and rd are logic low in parallel mode the output bus is enabled. in serial mode the rd line should be held low. wr / ref en/ disable write data/ reference enable/disable. when h /s sel pin is high both cs and wr are logic low db[15:8] are used to write data to the internal control register. when h /s sel pin is low this pin is used to enable or disabl e the internal reference. when h /s sel =0 and ref en/ disable = 0 the internal reference is disabled and an extern al reference should be applied to this pin. when h /s sel = 0 and ref en/ disable = 1 the internal reference is enabled. busy busy output. transitions high when a conver sion is started and remains high until the conversion is complete and the conversion data is latched into the output data registers. refin/refout reference input/output. the on-chi p reference is available on this pin for use external to the ad7658/ad7657/ad7656. alternatively, the internal reference can be disabled and an external reference applied to this input. see reference section. ser/ par serial/parallel selection input. when low, the parallel port is selected. when high the serial interface mode is selected. in serial mode db[ 10:8] take on their sdata [c:a] function, db[0:2] take on their dout select function, db[7] takes on its dcen function. in serial mode db15 and db[13:11] should be tied to dgnd. db[0]/sel a data bit [0]/select dout a. when ser/ par = 0, this pin acts as a three-state parallel digital output pin. when ser/ par is =1, this pin takes on its sel a fu nction, it is used to configure the serial interface. if this pin is 1, the serial interface will operate with one/two/three dout ouput pins and enables dout a as a serial output. wh en operating in serial mode this pin should always be = 1. db[1]/sel b data bit [1]/select dout b. when ser/ par = 0, this pin acts as a three-state parallel digital output pin. when ser/ par is =1, this pin takes on its sel b fu nction, it is used to configure the serial interface. if this pin is 1, the serial in terface will operate with two/three dout ouput pins and enables dout b as a serial output. if this pi n is 0 the dout b is not enabled to operate as a serial data output pin and only one dout output pin is used. db[2]/sel c data bit [2]/select dout c. when ser/ par = 0, this pin acts as a three-state parallel digital output pin. when ser/ par is =1, this pin takes on its sel c fu nction, it is used to configure the serial interface. if this pin is 1, the serial in terface will operate with three dout ouput pins and enables dout c as a serial output. if this pin is 0 the dout c is not enabled to operate as a serial data output pin. db[3]/dcin c data bit [3]/daisy chain in c. when ser/ par =0, this pin acts as a three-state parallel digital output pin. when ser/ par is =1 and dcen = 1, this pi n acts as daisy chain input c. db[4]/dcin b data bit [4]/daisy chain in b. when ser/ par =0, this pin acts as a three-state parallel digital output pin. when ser/ par is =1 and dcen = 1, this pin acts as daisy chain input b. db[5]/dcin a data bit [5]/daisy chain in a. when ser/ par is low, this pin acts as a three-state parallel digital output pin. when ser/ par is =1 and dcen = 1, this pi n acts as daisy chain input a. db[6]/sclk data bit [6[/serial clock. when ser/ par =0, this pin acts as thr ee-state parallel digital output preliminary technical data ad7658/ad7657/ad7656 rev. pri | page 13 of 25 pin. when ser/ par =1 this pin takes on its sclk input function, obtaining the read serial clock for the serial transfer. db[7]/hben/dcen data bit 7/ high byte enable / daisy chain enable. when opera ting in parallel word mode (ser/ par = 0 and w/ b = 1) this pin takes on its data bit 7 function. when operating in parallel byte mode (ser/ par = 0 and w/ b = 0), this pin takes on its hben function. when in this mode and the hben pin is a logic high, the data will be output msb byte first on db[15:8]. when the hben pin is a logic low the data will be output lsb byte first on db[15:8]. when operating in serial mode (ser/ par = 1) this pin takes on its dcen function. when dcen pin is a logic high the part will operate in daisy chain mode with db[5:3] taking on their dcin[a:c] function. db[8]/dout a data bit [8]/serial da ta output a. when ser/ par =0, this pin acts as a three-state parallel digital output pin. when ser/ par =1 and sel a = 1, this pin takes on its dout a function. db[9]/dout b data bit [9]/serial da ta output b. when ser/ par =0, this pin acts as a three-state parallel digital output pin. when ser/ par =1 and sel b = 1, this pin takes on its dout b function. this configures the serial interface to have two sdata output lines. db[10]/dout c data bit [10]/serial da ta output c. when ser/ par =0, this pin acts as a three-state parallel digital output pin. when ser/ par =1 and sel c = 1, this pin takes on its dout c function. this configures the serial interface to have three sdata output lines. db[11]/dgnd data bit [11]/digital ground. when ser/ par =0, this pin acts as a th ree-state parallel digital output pin. when ser/ par =1, this pin should be tied to dgnd. db[12:13], db[15] data bit [12:15]. ser/ par =0 these pins act as a three-stat e parallel digital input/output pins. when cs and rd are low these pins are used to output the conversion result. when cs and wr are low these pins are used to write to the control register. when ser/ par =1 these pins should be tied to dgnd. db[14]/refbuf en/ dis data bit [14]/ refbuf enable/ disable . when ser/ par =0, this pin acts as a three-state digital input/output pin. when ser/ par =1, this pin can be used to enable or disable the internal reference buffers. reset reset input. when set to a logic high , reset the ad7658/ad7657/ad7656. the current conversion if any is aborted. intern al register is set to all 0s. if not in use, this pin could be tied low. in hardware mode the ad7658/ad7657/ad 7656 will be configured depending on the logic levels on the hardware select pins. when operating in software mode a reset pulse is required afterpower up to select the default settings in the internal register. (see register section) range analog input range selection. logic input. the polarity on this pin will determine what input range the analog input channels will have. when this pin is a logic 1 at the falling edge of busy then range for the next conversion is 2 x vref. when this pin is a logic 0 at the falling edge of busy then range for the next conversion is 4 x vref. vdd positive power supply voltage. this is the positi ve supply voltage for the analog input section. 10 f and 100 nf decoupling capacitors should be placed on the vdd pin. vss negative power supply voltage. this is the ne gavtive supply voltage for the analog input section. 10 f and 100 nf decoupling capaci tors should be placed on the vss pin. stby standby mode input. this pin is used to put all six on-chi p adcs into standby mode. the stby pin is high for normal operatio n and low for standby operation. h /s sel hardware/software select input. logic input. when ser/ par =0 and this pin is a logic low the ad7658/ad7657/ad7656 operates in hardware select mode. the adc pairs to be simultaneously sampled are selected by the convst pins. when ser/ par =0 this pin is a logic high the adc pairs to be simultaneously samp led are selected by writing to the control register. w /b word/byte input. when this pin is a logic lo w data can be transfered to and from the ad7658/ad7657/ad7656 using the parall el data lines db[15:0]. when this pin is a logic high byte mode is enabled. in this mode data is transferred using da ta lines db[15:8], db[7] takes on its hben function. to obtain the 12/14/16-bit con version result two byte reads are required. ad7658/ad7657/ad7656 preliminary technical data rev. pri | page 14 of 25 terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. bipolar zero code error it is the deviation of the midscale transition (all 1s to all 0s) from the ideal v in voltage, i.e., agnd - 1 lsb. positive full scale error it is the deviation of the last code transition (011110) to (011111) from the ideal ( +4 x v ref - 1 lsb, + 2 x v ref C 1 lsb) after the bipolar zero code error has been adjusted out. negative full scale error this is the deviation of the first code transition (10000) to (10001) from the ideal (i.e., - 4 x v ref + 1 lsb, - 2 x v ref + 1 lsb) after the bipolar zero code error has been adjusted out. track-and-hold acquisition time the track-and-hold amplifier returns to track mode at the end of conversion. the track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1 lsb, after the end of the conversion. see the track-and-hold section for more details. signal-to-(noise + distortion) ratio this is the measured ratio of signal-to-(noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency ( f s /2, excluding dc). the ratio depends on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by signal-to- ( noise + distortion ) = (6.02 n + 1.76) db thus, for a 12-bit converter, this is 74 db, for a 14-bit converter, this is 86 db and for a 16-bit converter, this is 98 db. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. for the ad7658/ad7657/ad7656, it is defined as 1 2 6 2 5 2 4 2 3 2 2 log 20 ) ( v v v v v v db thd + + + + = where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m , n = 0, 1, 2, 3. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second-order terms include (fa + fb) and (fa ? fb), while the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ?2fb). the ad7658/ad7657/ad7656 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. preliminary technical data ad7658/ad7657/ad7656 rev. pri | page 15 of 25 converter details the ad7658/ad7657/ad7656 are high-speed, low power converters that allow the simultaneous sampling of their six on- chip adcs. the analog inputs on the ad7658/ad7657/ad7656 can accept true bipolar input signals, the range pin/rng bits are used to select between 4 x vref or 2 x vref as the input range for the next conversion. the ad7658/ad7657/ad7656 contain six sar adcs, six track-and-hold amplifiers, on-chip 2.5v reference, reference buffers, high speed parallel and serial interfaces. the ad7658/ad7657/ad7656 allow the simultaneous sampling of all six adcs when all three convst signals are tied together. alternatively the six adcs can be grouped into three pairs. each pair has an associated convst signal used to initiate simultaneous sampling on each adc pair, on four adcs or all six adcs. convsta is used to initiate simultaneous sampling on v1 and v2, convstb is used to initiate simultaneous sampling on v3 and v4, and convstc is used to initiate simultaneous sampling on v5 and v6. a conversion is initiated on the ad7658/ad7657/ad7656 by pulsing the convstx input. on the rising edge of convstx the track-and-hold on the selected adcs will be placed into hold mode and the conversions are started. after the rising edge of convstx the busy signal will go high to indicate the conversion is taking place. the conversion clock for the part is internally generated and the conversion time for the ad7658/ad7657/ad7656 is 3 s from the rising edge of convstx. the busy signal will return low to indicate the end of conversion. on the falling edge of busy the track-and-hold will return to track mode. data can be read from the output register via the parallel or serial interface. track-and-hold section the track-and-hold amplifiers on the ad7658/ad7657/ad7656 allow the adcs to accurately convert an input sine wave of full-scale amplitude to 12/14/16- bit resolution. the input bandwidth of the track-and-hold amplifiers is greater that the nyquist rate of the adc even when the ad7658/ad7657/ad7656 is operating at its maximum throughput rate. the ad7658/ad7657/ad7656 can handle input frequencies up to 8 mhz. the track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of convstx. the aperture time for the track-and-hold, (i.e. the delay time between the external convstx signal actually going into hold), is typically 20ns. this is well matched across all six track-and-holds on the one device and also from device to device. this allows more than six adcs to be simultaneo usly sampled. the end of the conversion is signaled by the falling edge of busy and its at this point the track-and-holds return to track mode and the acquisition time begins. analog input section the ad7658/ad7657/ad7656 can handle true bipolar input voltages. the logic level on the range pin or the value written to the rngx bits in the control register will determine the analog input range on the ad7658/ad7657/ad7656 for the next conversion. when the range pin/ rngx bit is 1 the analog input range for the next conversion is 2 x vref, when the range pin/ rng bit is 0 the analog input range for the next conversion is 4 x vref. d d v dd c2 r1 v1 v ss c1 figure 3. equivalent analog input structure figure 3 shows an equivalent circuit of the analog input structure of the ad7658/ad7657/ad7656. the two diodes, d1 and d2, provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the v dd and v ss supply rails by more than tbd mv. this will cause these diodes to become forward-biased and to start conducting current into the substrate. the maximum current these diodes can conduct without causing irreversible damage to the part is 10 ma. capacitor c1 in figure 3 is typically about 5 pf and can be attributed primarily to pin capacitance. resistor r1 is a lumped component made up of the on resistance of a switch (track-and-hold switch). this resistor is typically about 25 ?. capacitor c2 is the adc sampling capacitor and has a capacitance of 25 pf typically. ad7658/ad7657/ad7656 preliminary technical data rev. pri | page 16 of 25 adc transfer function the output coding of the ad7658/ad7657/ad7656 is twos complement. the designed code transitions occur midway between successive integer lsb values, i.e., 1/2 lsb, 3/2 lsbs. the lsb size is fsr/4096 for the ad7658, fsr/16384 for the ad7657 and fsr/65536 for the ad7656. the ideal transfer characteristic for the ad7658/ad7657/ad7656 is shown in figure 4. 000...000 - fsr/2 + 1/2lsb adc code analog input 011...111 100...001 100...010 011...110 000...001 111...111 +fsr/2 - 3/2lsb 100...000 agnd - 1lsb figure 4. ad7658/ad7657/ad7656 transfer characteristic the lsb size is dependant on the analog input range selected. see table 7. reference section the vref pin either provides access to the ad7658/ad7657/ad7656s own 2.5v reference or allows for an external reference to be connected providing the reference source for the ad7658/ad7657/ ad7656 conversions. the ad7658/ad7657/ad7656 can accommodate a 2.5v to 3v external reference range. when using an external reference the internal reference needs to be disabled. after a reset the ad7658/ad7657/ad7656 defaults to operating in external reference mode. the internal reference can be enabled in either hardware or software mode. to enable the internal reference in hardware mode, h /s sel pin =0 and the ref en/ disable = 1. to enable the internal reference in software mode h /s sel pin =1, a write to the control register is necessary to make db1 of the register = 1. the refin/out pin should be decoupled using 10 f and 100 nf capacitors. the ad7656 contains three on-chip reference buffers. each of the three adc pairs has an associated reference buffer. these reference buffers require external decoupling caps on ref cap a, ref cap b, and ref cap c pins. 10 f and 100 nf decoupling capacitor should be placed on these ref cap pins. table 7. lsb sizes for each analog input range ad7656 ad7657 ad7658 input range 10v 5v 10v 5v 10v 5v fs range 20v/65536 10v/65536 20v/16384 10v/16384 20v/4096 10v/4096 lsb size 0.305 mv 0.152 mv 1.22 mv 0.61 mv 4.88 mv 2.44 mv ! "" "" "" # # $ # % % ! & ' # # $ " ()(" # *+ $ $ (, -+ + ! .-+ .+ ! # $// / $ " " ()(" " $ ),0 ("( $( $ 1( () $# $ )0 %2 3 $ 4(( figure 5. ad7658/ad7657/ad7656 typical connection diagram. note 1: decoupling shown on the av cc pin applies to each av cc pin. preliminary technical data ad7658/ad7657/ad7656 rev. pri | page 17 of 25 interface section the ad7658/ad7657/ad7656 provides two interface options, a parallel interface and a high speed serial interface. the required interface mode is selected via the ser/ par pin. the parallel interface can operate in word (w/ b = 1) or byte (w/ b = 0) mode. the interface modes are discussed in the following sections. parallel interface (ser/ par = 0) the ad7658/ad7657/ad7656 consist of six 12/14/16-bit adcs. a simultaneous sample of all six adcs can be performed by connecting all three convst pins together, convsta, convstb, convstc. the rising edge of convstx initiates simultaneous conversions on the selected adcs. the ad7658/ad7657/ad7656 contains an on-chip oscillator that is used to perform the conversions. the conversion time, t conv , is 3 s. the busy signal goes low to indicate the end of conversion. the falling edge of the busy signal is used to place the track-and-hold into track mode. the ad7658/ad7657/ad7656 also allow the six adcs to be simultaneously converted in pairs by pulsing the three convst pins independently. convsta is used to initiate simultaneous conversions on v1 and v2, convstb is used to initiate simultaneous conversions on v3 and v4, and convstc is used to initiate simultaneous conversions on v5 and v6. the conversion results from the simultaneously sampled adcs are stored in the output data registers. data can be read from th e ad7658/ad7657/ad7656 via the parallel data bus with standard cs and rd signals ( w /b = 0). to read the data over the parallel bus ser/ par should be tied low. the cs and rd input signals are internally gated to enable the conversion result onto the data bus. the data lines db0 to db15 leave their high impedance state when both cs and rd are logic low. the cs signal can be permanently tied low and the rd signal can be used to access the conversion results. a read operation can take place after the busy signal goes low. the number of read operations required will depend on the number of adcs that were simultaneously sampled, see figure 5. if convsta and convstb were brought low simultaneously, four read operations are required to obtain the conversion results from v1, v2, v3 and v4. the conversion results will be output in ascending order. for the ad7657 db15 and db14 will contain two leading zeros and db[13:0] will output the 14-bit conversion result. for the ad7658 db[15:12] will contain four leading zeros and db[11:0] will output the 12- bit conversion result. if there is only an 8-bit bus available the ad7658/ad7657/ad7656 interface can be configured to operate in byte mode ( w /b= 1). in this configuration the db7/hben/dcen pin takes on its hben function. the conversion results from the ad7658/ad7657/ad7656 can be accessed in two read operations with 8-bits of data provided on db15 to db8 for each of the read operations, see figure 6. the hben pin determines whether the read operation accesses the high byte or the low byte of the 12/14/16-bit conversion result first. to always access the low byte first on db15 to db8, the hben pin should be tied low. to always access the high byte first on db15 to db8 then the hben pin should be tied high. in byte mode when all three convst pins are pulsed together to initiate simultaneous conversions on all six adcs, twelve read operations are necessary to read back the six 12/14/16-bit conversion results when operating in byte mode. db[6:0] should be left unconnected in byte mode. the ad7658/ad7657/ad7656 allow the option of reading during a conversion. if for example, a simultaneous conversion had occurred on v1 and v2 by pulsing the convsta pin. the processor will next read the conversion results from the ad7658/ad7657/ad7656. during the read operation after the busy signal has gone low further simultaneous conversions can be initiated by pulsing the convst pins. however to achieve the specified performance from the ad7658/ad7657/ad7656 reading after the conversion is recommended. * & 5 " 6)6" ),0 " $ ad7658/ad7657/ad7656 preliminary technical data rev. pri | page 18 of 25 figure 6. ad7658/ad7657/ad7656 parallel interface timing diagram ( w /b= 0) low byte high byte db15-db8 t 3 t 4 t 5 t 6 t 7 t 9 figure 7. parallel interface C read cycle for byte mode of operation. ( w /b= 1, hben = 0) software selection of adcs the h /s sel pin determines the source of the combination of adcs that are to be simultaneously sampled. when the h /s sel pin is a logic low the combination of channels to be simultaneously sampled is determined by the convsta, convstb, and convstc pins. when the h /s sel pin is a logic high the combination of channels selected for simultaneous sampling is determ ined by the contents of the control register db15 to db8. in this mode a write to the control register is necessary. the control register is an 8-bit write only register. data is written to this register using the cs and wr pins and db[15:8] data pins, see figure 8. the control register is shown in table 8. to select an adc pair to be simultaneously sampled, set the corresponding data line high during the write operation. the ad7658/ad7657/ad7656 control register allows individual ranges to be programmed on each adc pair. db12 to db10 in the control register are used to program the range on each adc pair. the ad7658/ad7657/ad7656 allows the user to select either 4 x vref or 2 x vref as the analog input range. rnga is used to select the range for the next conversion on v1 and v2, rngb is used to select the range for the next conversion on v3 and v4 and rngc is used to select the range for v5 and v6. when the rngx is 1 the range on the corresponding analog input pair is 2 x vref. when the rngx bit is 0 the range on the corresponding analog input pair is 4 x vref. the refen pin is used to disable the internal reference, allowing the user to supply an external reference to the ad7658/ad7657/ad7656. when a 0 is written to this bit the on-chip reference is disabled. when a 1 is written to this bit the on-chip reference is enabled. the ref buf bit is used to disable the internal reference buffers. when this bit is 1 the internal reference buffers are disabled. after a reset occurs on the ad7658/ad7657/ad7656 the control register will contain all zeros. table 8.control register d15 d14 d13 d12 d11 d10 d9 d8 vc vb va rngc rngb rnga refen refbuf the convsta signal is used to initiate a simultaneous conversion on the combination of channels selected via the control register. the convstb and convstc signals can be tied low when operating in software mode, h /s sel = 1. the number of read pulses required will depend on the number of adcs selected in the control register and also whether operating in word or byte mode. the conversion results will be output in ascending order. during the write operation the data bus bits db15 to db8 are bidirectional and become inputs to the control register when rd is a logic high, cs and wr are logic low. the logic state on db15 through db8 is latched into the control register when wr goes logic high. t 12 data db15-db8 t 13 t 14 t 15 t 16 figure 8. parallel interface C write cycle for word mode . ( w /b= 0) changing the analog input range( h /s sel=0) the ad7658/ad7657/ad7656 range pin allows the user to select either 2 x vref or 4 x vref as the analog input range for the six analog inputs. when the h /s sel pin is low the logic state of the range pin is sampled on the falling edge of the busy signal to determine the range for the next simultaneous conversion. when the range pin is a logic high at the falling edge of the busy signal the range for the next preliminary technical data ad7658/ad7657/ad7656 rev. pri | page 19 of 25 conversion is 2 x vref. when the range pin is a logic low at the falling edge of the busy signal the range for the next conversion is 4 x vref. changing the analog input range( h /s sel=1) when the h /s sel pin is high the range can be changed by writing to the control register. db12:10 in the control register are used to select the analog input ranges for the next conversion. each analog input pair has an associated range bit, allowing independent ranges to be programmed on each adc pair. when the rngx bit is 1 the range for the next conversion is 2 x vref. when the rngx bit is 0 the range for the next conversion is 4 x vref. serial interface (ser/ par = 1) by pulsing one, two or all three convstx signals the ad7658/ad7657/ad7656 will simultaneously convert the selected channel pairs on the rising edge of convstx. the simultaneous conversions on the selected adcs are performed using the on-chip trimmed oscillator. after the rising edge of convstx the busy signal goes high to indicate the conversion has started. it returns low when the conversion is complete 3 s later. the output register will be loaded with the new conversion results and data can be read from the ad7658/ad7657/ad7656. to read the data back from the ad7658/ad7657/ad7656 over the serial interface ser/ par should be tied high. the cs and sclk signal are used to transfer data from the ad7658/ad7657/ad7656. the ad7658/ad7657/ad7656 has three dout pins, douta, doutb, doutc. data can be read back from the ad7658/ad7657/ad7656 using one, two or all three dout lines. figure 9 shows six simultaneous conversions and the read sequence using three dout lines. in figure 8, 32 sclk transfers are used to access data from the ad7658/ad7657/ad7656, two 16 sclk transfers individually framed with the cs signal can also be used to access the data on the three dout lines. when operating the ad7658/ad7657/ad7656 in serial mo de with conversion data being clocked out on all three dout line db0-db2 should be tied to v drive . these pins are used to enable the douta C doutc lines respectively. if it is required to clock conversion data out on two data out lines then douta and doutb should be used. again to enable douta and doutb, db0 and db1 should be tied to v drive and db2 should be tied low. when six simultaneous conversions are performed and only two dout lines are used, a 48 sclk transfer can be used to access the data from the ad7658/ad7657/ad7656. the read sequence is shown in figure 10 for a simultaneous conversion on all six adcs using two dout lines. if a simultaneous conversion occurred on all six adcs and only two dout lines are used to read the results from the ad7658/ad7657/ad7656, douta will clock out the result from v1, v2 and v5, while doutb will clock out the results from v3,v4 and v6. data can also be clocked out using just one dout line, in this case douta should be used to access the conversion data. to configure the ad7658/ad7657/ad7656 to operate in this mode then db0 should be tied to v drive , db1 and db2 should be tied low. the penalty for using just one dout line is the throughput rate will be reduced. data can be accessed from the ad7658/ad7657/ad7656 using one 96 sclk transfer, three 32 sclk individually framed transf ers or six 16 sclk individually framed transfers. in serial mode the rd signal should be tied low. * " 6)6" ),0 " , ,) ," &* & 5 "/7 figure 9. serial interface with three dout lines. ad7658/ad7657/ad7656 preliminary technical data rev. pri | page 20 of 25 * " , ,) 54 & 5 "/7 figure 10. serial interface with two dout lines. serial read operation figure 11 shows the timing diagram for reading data from the ad7658/ad7657/ad7656 in serial mode. the sclk input signal provides the clock source for the serial interface. the cs signal goes low to access data from the ad7658/ad7657/ad7656. the falling edge of cs takes the bus out of three-state and clocks out the msb of the 12/14/16-bit conversion result. the adcs output 16- bits for each conversion result. the data stream of the ad7658 consists of four leading zeros followed by 12 bits of conversion data provided msb first; the data stream of the ad7657 consists of two leading zeros, followed by the 14-bits of conversion data provided msb first; the data stream of the ad7656 consists of sixteen bits of conversion data provided msb first. the first bit of the conversion result is valid on the first sclk falling edge after the cs falling edge. the subsequent 15 data bits of the data are clocked out on rising edge of the sclk signal. data is valid on the sclk falling edge. sixteen clock pulses must be provided to the ad7658/ad7657/ad7656 to access each conversion result. figure 11 shows how a 16 sclk read is used to access the conversion results. " ()(" ),0 "8, " $ "8, "/7 " ,()(" ) )5 )& ) ) figure 11. serial read operation daisy-chain mode(dcen =1, ser/ par = 1) when reading conversion data back from the ad7658/ad7657/ad7656 using the three/two dout pins it is possible to configure the ad7658/ad7657/ad7656 to operate in daisy-chain mode, using the dcen pin. this daisy-chain feature allows multiple ad7658/ad7657/ad7656 devices to be cascaded together. this feature is useful for reducing component count and wiring connections. an example connection of two devices is shown in figure 12, this configuration shows two dout lines being used. simultaneous sampling of the 12 analog inputs is possible by using a common convst signal. the db5, db4 and db3 data pins are used as data input pins, dcin[a:c], for the daisy-chain mode. the rising edge of convst is used to initiate a conversion on the ad7658/ad7657/ad7656. after the busy signal has gone low to indicate the conversion is complete the user can begin to read the data from the two devices. figure 13 shows the serial timing diagram when oper ating two ad7658/ad7657/ad7656 preliminary technical data ad7658/ad7657/ad7656 rev. pri | page 21 of 25 devices in daisy chain mode. the cs falling edge is used to frame the serial transfer from the ad7658/ad7657/ad7656 devices, take the bus out of three- state and clock out the msb of the first conversion result. in the example shown all twelve adc channels were simultaneously sampled. two dout line are used to read the conversion results in this example. cs frames a 96 sclk transfer. during the first 48 sclk the conversion data is transferred from device #2 to device #1. dout a on de vice #2 transfers conversion data from v1, v2 and v5 into dcina in device #1. dout b on device #2 transfers conversion results from v3, v4 and v6 to dcin b in device #1. during the first 48 sclk device #1 transfers data into the digital host, douta on device #1 transfers conversion data from v1, v2 and v5. doutb on device #1 transfers conversion data from v3, v4 and v6. during the last 48 sclks device #2 will clock out zeros, device #1 will shift the data it clocked in from device #2 during the first 48 sclks into the digital host. this example could also have been implemented using 3 x 32 sclk individually framed sclk transfers or 6 x 16 sclk individually framed sclk transfers provided dcen remained high during the transfers. figure 14 shows the timing if two ad7656 were configured in daisy chain mode but operating with three dout lines. again assuming a simultaneous sampling of all 12 inputs occurred. during the read operation the cs frames a 64 sclk transfer. during the first 32 sclks of this transfer the conversion results from device #1 are clocked into the digital host and the conversion results from device #2 are clocked into device #1. during the last 32 sclks of the transfer the conversion results from device #2 are clocked out of device #1 and into the digital host. device #2 will clock out zeros. % %13 " $ " "/7 " " " " "/7 "/7 * , ,) , ,) " " ) " 9 " 9 " : " :* figure 12. daisy-chain configuration " :, ;) /) ;) * /) * ;) /) ;) /) ;) * /) ;) /) ;) * /) * ;) /) * & " ()(" ),0 "/7 " & &* && 5 54 5- & 5 -5 - - " :,) ;) & /) & ;) 5 /) 5 ;) /) ;) & /) & ;) 5 /) " :*, ;) & /) & ;) 5 /) 5 ;) /) " :*,) figure 13. daisy-chain serial interface timing with 2 dout lines ad7658/ad7657/ad7656 preliminary technical data rev. pri | page 22 of 25 " :, ;) /) ;) * /) * ;) /) ;) * /) * * & " ()(" ),0 "/7 " & &* && 5 54 5- & 5 " :,) ;) & /) & ;) 5 /) 5 ;) & /) & ;) 5 /) 5 ;) /) ;) * /) * " :*, ;) & /) & ;) 5 /) 5 " :*,) " :," ;) /) ;) /) ;) /) ;) /) ;) /) ;) /) " :*," figure 14. daisy-chain serial interface timing with 3 dout lines preliminary technical data ad7658/ad7657/ad7656 rev. pri | page 23 of 25 standby/partial power down modes of operation each adc pair can be individually placed into partial power down by bringing the convstx signal low before the falling edge of busy. to power the adc pair back up again then the convstx signal should be brought high to tell the adc pair to power up and place the track-and-hold into track mode. in partial power down mode the reference buffers will remain powered up. while an adc pair is in partial power down, conversions can still occur on the other adcs. the ad7658/ad7657/ad7656 has a standby mode whereby the device can be placed into a low current consumption mode (0.5 a max). the ad7658/ad7657/ad7656 is placed into standby mode by bringing the logic input stby low. the ad7658/ad7657/ad7656 can be powered up again for normal operation by bringing stby logic high. the output data buffers are still operational when the ad7658/ad7657/ad7656 is in standby. this means the user can still continue to access the conversion results when the ad7658/ad7657/ad7656 is in standby. this standby feature can be used to reduce the average power consumed by the ad7658/ad7657/ad7656 when operating at lower throughput rates. the ad7658/ad7657/ad7656 could be placed into standby at the end of each conversion when busy goes low and taken out of standby again prior to the next conversion. the time it takes for the ad7658/ad7657/ad7656 to come out of standby is called the wake-up time. this wake-up time will limit the maximum throughput rate at which the ad7658/ad7657/ad7656 can operate when powering down between conversions. ad7658/ad7657/ad7656 preliminary technical data rev. pri | page 24 of 25 application hints layout the printed circuit board that houses the ad7656 should be designed so the analog and digital sections are separated and confined to certain areas of the bo ard. this facilitates the use of ground planes that can be easily separated. digital and analog ground planes should be joined in only one place, preferably underneath the ad7656, or, at leas t, as close as possible to the ad7656. if the ad7656 is in a system where multiple devices require analog to digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the ad7656. it is recommended to avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allo wed to run under the ad7656 to avoid noise coupling. fast switching signals like convst or clocks should be shie lded with digital grou nd to avoid radiating noise to other sections of the board and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on di fferent but close layers of the board should run at ri ght angles to each other. this will reduce the effect of feedthrough through the board. the power supply lines to the ad7656 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the supplies impedance presented to the ad7656 and to reduce the magnitude of the supply spikes. decoupling cerami c capacitors, typically 100 nf, should be placed on all of the power supply pins, power supplies pins v dd , v ss , av cc , dv cc , and v drive . the decoupling capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. additionally, low esr 10 f capacitors should be located in the vicinity of the adc to further reduce low frequency ripple. the decoupling capacitors should be close to the adc and connected with short and large traces to minimize parasitic inductances. preliminary technical data ad7658/ad7657/ad7656 rev. pri | page 25 of 25 outline dimensions 64-lead low profile quad flat package [lqfp] (st-64) dimensions shown in millimeters ordering guide ad7658/ad7657/ad7656 products temperature package package description package outline ad7658bstz 1 C40c to +85c lqfp st-64 AD7658BSTZ-REEL 1 C40c to +85c lqfp st-64 ad7657bstz 1 C40c to +85c lqfp st-64 ad7657bstz-reel 1 C40c to +85c lqfp st-64 ad7656bstz 1 C40c to +85c lqfp st-64 ad7656bstz-reel 1 C40c to +85c lqfp st-64 eval- ad7656cb 2 evaluation board eval-control brd2 3 controller board notes 1 z = pb-free part. 2 this can be used as a stand-alone evaluation board or in conjunction with the eval-control board for evaluation/demonstration purposes. 3 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in th e cb designators. to order a complete evaluation kit, the particular adc eval uation board, e.g., eval-ad 7658/ad7657/ad7656cb, the eval-control brd2, and a 12v transf ormer must be ordered. see relevant evaluation board technical note for more information. |
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